J-Link is a debug probe for embedded systems, supporting JTAG, SWD, and SWO interfaces.
Field note
J-Link is a debug probe from SEGGER, used for debugging and programming embedded systems. It supports JTAG, SWD, and SWO interfaces, and is compatible with various IDEs.
Capabilities
Tags
Ways to use it
Not filed / https://kb.segger.com/UM08001_J-Link_/_J-Trace_User_Guide
Not filed / Not filed
Not filed / Not filed
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Product features
Allows sending commands to J-Link via command strings.
Includes bypass and boundary-scan registers.
Uses DCC (Debug Communications Channel) for memory access.
Supports breakpoints in flash memory.
Holds current instruction for test selection.
Automated flash programming, verification, and production-oriented workflows.
Command-line interface for target connection, flash programming, memory and register access, and execution control.
Provides GDB Remote Protocol interface for debugging with breakpoints, stepping, register access, and memory inspection.
High-speed bidirectional communication for logs, test results, and runtime info without extra serial interface.
Enables deep integration of J-Link functionality into custom development tools.
Supports debugging in low power modes.
Supports debugging multiple cores in a single target system.
Provides various reset strategies for target devices.
Supports custom script files for advanced debugging.
Supports semihosting for I/O operations.
Support for multiple devices on SWD bus.
JTAG defines a TAP with TDI, TCK, TMS, TDO, and optional nTRST.
A synchronous finite-state machine controlling test operations.